Implementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters

Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for highperformance circuits due to their small area overhead and simple control circuitry. When compared to other pattern generators TRC often requires long test time to achieve high fault coverage and large storage space to store required control data and TRC seeds. Programmable Twisted Ring Counter-based on-chip test generation scheme is to minimize both the required test time and test data volume. Programmable Twisted Ring Counter operates on test per clock method to reduce the test time. To reduce the storage data for testing, seed and control vector determination process is used to achieve the less storage data in ROM.